| 1. | 9 months | Study of Integration of layout equivalent results with switching amplifier. | Simulation results for integrated design. |
Delivered
|
| 2. | 12 months | Analysis of parasitic, transmission line (TL) test structures and connectors on PCB. |
Model and de-embedding techniques for connectors, parasitic and TL structures obtained through measurement. |
Delivered
|
| 3. | 15 months | First tape-out of Power Amplifier (PA) and on-chip test structures |
GDSII files of the design for first tape out. |
Delivered
|
| 4. | 18 months | PCB designing for the PA sent for fabrication |
Fabricated PCB for the PA. |
Delivered
|
| 5. | 21 months | Test and measurement of fabricated design and on-chip test structures. |
Measured results for fabricated IC mounted on PCB. |
Delivered
|
| 6. | 24 months | RF signal generation compliant with high speed wireless standards. |
Measurement of fabricated chip with RF signals compliant with high speed. |
Delivered
|
| 7. | 27 months | Design of second Power Amplifier (PA) using measured results from PA and test structures.
RFMEMS based matching network design (subject to consent from METU).
. |
Simulation results for PA with model parameters from measurement.
Simulation results of PA with RFMEMS based network (subject to consent from METU).
|
In progress
|
