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Evaluation of Silterra's 130nm RFIC Technology for Power Amplifier Design

    SilTerra is a fast-growing wafer foundry provider based in Malaysia, which offers cost-effective CMOS wafer technology to global semiconductor customers. It currently offers up to 60-70% cost reduction in IC fabrication as compared to IBM's CMOS IC technology. Electronics Design Center, NED UET, which has been designing ICs using IBM's technology, is now given access to Silterra's 130 nm technology and researchers at EDC intend to use it for implementing their future designs. However, before adopting a new technology, an IC designer must first evaluate the viability of its use for designing some specific range of circuits. In the proposed project, our task is to provide EDC with a justifiable evaluation of the pros and cons of adopting Silterra's technology for their future Power Amplifier designs. We shall design a fully integrated differential Class-E power amplifier in Silterra's 130 nm technology and compare its performance parameters with those of a similar existing design implemented with IBM's equivalent technology. The project aims to design a PA chip with performance similar to the existing design in terms of efficiency, bandwidth, output power etc. with considerably lower cost. The driving stage and output balun will also be integrated on-chip with the main amplifying stage. Cadence RF Design tools will be used for schematic entry, layout design and verification whereas Sonnet will be used for EM simulations.

    Student Members

    Ifrah Jaffri (ifrahjaffri@yahoo.com) Sonia Kanwal
    Usama Ahmed Siddiqui (usama.ahmed.siddiqi@gmail.com) Urooj Sajid
    Faizan Hadi (faizan_hadi@hotmail.com) Urooj Sajid
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